1. Field of Invention
The present invention relates to a method for manufacturing interconnects. More particularly, the present invention relates to a method for manufacturing interconnects using a dual damascene process.
2. Description of Related Art
In the fabrication of very large scale integrated (VLSI) circuits, semiconductor devices are generally linked by several metallic interconnecting layers commonly referred to as multilevel interconnects. As the level of circuit integration continues to increase, manufacturing processes are complicated and product yield and reliability is harder to maintain. Dual damascene process is a convenient method for forming multilevel interconnects. Principally, the process includes etching a dielectric layer to form trenches, and then depositing metal into the trenches to form the interconnects. The dual damascene process is capable of producing highly reliable interconnects with a relatively high product yield. Due to its versatility, the dual damascene process has become a predominant method for fabricating interconnects. However, several drawbacks in the method still need to be resolved. For example, photoresist (PR) that remains inside a via hole after a photolithographic operation may affect the profile of the via hole.
FIGS. 1A through 1C are schematic, cross-sectional views showing the steps taken in carrying out a conventional dual damascene process for fabricating interconnects. As shown in FIG. 1A, a semiconductor substrate 100 having a metallic layer 102 therein is provided. A silicon nitride layer 104 having a thickness of about 500 .ANG. to 1000 .ANG. is formed over the substrate 100. An inter-layer dielectric layer 106 having a thickness of about 9000 .ANG. to 16000 .ANG. is formed over the silicon nitride layer 104. A patterned photoresist layer 108 is formed over the inter-layer dielectric layer 106 using photolithographic techniques. Using the patterned photoresist layer 108 as a mask, the dielectric layer 106 is etched to form a via hole 110.
As shown in FIG. 1B, the photoresist layer 108 is removed. Meanwhile, another photoresist layer 112 to define the metal trench is formed over the inter-layer dielectric 106. Some of the photoresist material is also deposited into the via hole 110. The photoresist layer 112 is patterned by removing some photoresist material. However, some photoresist material inside the via hole 110 remains and forms a residual photoresist layer 112a.
As shown in FIG. 1C, using the photoresist layer 112 as a mask, an anisotropic etching operation is conducted to form trenches 114 inside the inter-layer dielectric 106. Subsequent processing steps are not shown in the figure because those steps should be familiar to the people in the semiconductor field. In brief, subsequent steps includes the removal of the photoresist layer 112, deposition to form a barrier layer and a copper layer and a final planarization using a chemical-mechanical polishing (CMP) method.
As shown in FIG. 1C, due to the difficulties in removing away some of the dielectric material in the neighborhood of the residual photoresist 112a, an undesirable trench profile is often created. In addition, the dielectric layer 106 is typically a silicon dioxide layer, which is a transparent material. Therefore, an anti-reflection coating is frequently required. However, the formation of the silicon nitride layer 104 as an anti-reflection coating between the metallic layer 102 and the dielectric layer 106 is far from ideal.